1. Field
Example embodiment relate to a semiconductor memory device and method of forming a semiconductor memory device, for example, to a semiconductor memory device capable of equalizing load of a coupling capacitance between a line and a component in a memory cell array when the line intersects the component.
2. Description of Related Art
FIG. 3 is a schematic view of a memory cell array 100 in a semiconductor memory device. The memory cell array 100 may include a plurality of memory cells (not shown) disposed in a matrix form, and a plurality of word lines and bit lines may be disposed in the memory cell array 100. A word line and a bit line may be selected by outputs of an X decoder 301 and a Y decoder 302, and a memory cell located at intersection therebetween may be selected.
A memory region with a memory cell array may be decreased as the size of a memory cell becomes smaller. FIG. 1A illustrates a memory cell region and a peripheral region and FIG. 1B illustrates a reduced memory cell region and a reduced peripheral region. As illustrated in FIGS. 1A and 1B, the degree of reduction of the peripheral region is relatively small, when compared with the degree of reduction of the memory cell region. The reason is that the size of a circuit and the number of signal lines increases as a semiconductor device with higher performance and/or lower power consumption may be required.
Referring to FIG. 2, a semiconductor chip 10 may include, for example, memory cell regions 101 and 102 and peripheral circuits 201, 202, 203 and 204. When a signal used for each peripheral circuit is not synchronized with an operation of a memory cell, this may affect a word line or a bit line, and thus only the word line and the bit line may be formed in the memory cell region 101 and other signal lines may not be formed.
Lines between the peripheral circuits 201, 202, 203 and 204 may be formed such that the lines do not pass over the memory cell regions 101 and 102. Referring to FIG. 4, digital signal processors (DSPs) 211 and 212 and memory control units (MCUs) 213 and 214 are exemplarily illustrated as peripheral circuits in a chip 20.
Even though the DSPa 211 and the MCUa 213 are disposed to interpose a memory a 111 (for example, a flash memory) therebetween, a line connecting them may not pass over and detours around the memory a 111. Similarly, even though the DSPb 212 and the MCUb 214 may be disposed to interpose a memory b 112 (for example, a flash memory) therebetween, a line connecting them may not pass over and detours around the memory b 112. In FIG. 4, these lines are represented by relatively thick arrows 401 and 402.
When lines are formed so as to detour memory cell regions without passing over them, a line region of a peripheral region may increase according to an increase in the number of signals. Therefore, it may be difficult to reduce the peripheral region around the memory cell regions.
Reduction of a die size may be essential to a general-purpose memory. Also, a signal line may need to be formed in a memory cell of a peripheral circuit. For example, as described above, when memories (for example, flash memories) and MCUs are mounted in the same chip, signal lines may be formed as well as word lines and/or bit lines in a memory cell, as lines 501 and 502 are illustrated in FIG. 5. In FIG. 5, the line 501 intersects a memory 111 to connect a DSPa 211 with a MCUa 213 and the line 502 intersects a memory 112 to connect a DSPb 212 with a MCUb 214 on a chip 20. In this case, lines may be formed as illustrated in FIGS. 10A and 10B.
For example, when a transmitting point A and a receiving point B of a signal are located as illustrated in FIG. 10A, an A-B line 600 between the transmitting point A and the receiving point B may be at right angles to bit lines BL0-BL2, is bent at two portions of a bit line BL2, and is at right angles to bit lines BL2-BL4, as illustrated in FIG. 10B.
In a memory cell array, the bit line BL2 corresponding to a lower one of bent portions of the line 600 may be affected by load of coupling capacitance between the line 600 and the bit lines BL0˜BL4. Therefore, coupling capacitances of the bit lines BL0˜BL4 are represented as follows: BL0, BL4<BL1, BL3<BL2.
In a semiconductor memory device, the read access speed should be considered, based on a line that is most affected by load of a coupling capacitance, e.g., a line with the slowest read access speed. Therefore, in FIGS. 10A and 10B, the read access speed may be determined based on the bit line BL2 that has the largest coupling capacitance. That is, the read characteristic may be deteriorated due to biased coupling capacitance in the bit lines.
As shown in FIG. 10B and discussed above, when coupling capacitances between adjoining word lines or bit lines are not uniform, it may become difficult to accurately operate the semiconductor memory device.